Adder



14 Sheets-Sheet l J. M. PUGMIRE ADDER Ndo .004 .umm H July zo, 1965Filed May 3, 1961 wam .S

NVENTOR JOHN H. PUGMIRE BY ATTORNEY J. M. PUGMIRE July 20, 1965 ADDER 14Sheets-Sheet 2 Filed May 3. 1961 EEE 5 o E@ o Q E@ o c v .Se D N So o To04m:

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c1 o P2 C2 6 To sum sus CARRY ADJUST FUNCTION COMBINER July 20, 1965SUMMATION TERM GEN ERATOR l50 is,

ERROR 314 FIG.15 CARRY DUFUCATE F|G.15 COMPARE ADDER 4 J. M. PUGMIREJuly 20, 1965 ADDER 14 Sheets-Sheet 4 Filed May 3, 1961 FIG.4

INSTRUCTION WORD IIIDEXING WDRD ADDRESS CONTROL OPERATION CODE SINDICATES SIGN DATA WORD FIG.5

FIG.6a

2/5 CODE DECIMAL DIGIT DECIMAL s's s coMPLEMENT FIG.6b

6 o 0 o O UIHIM -Hzwl ,MIMIMIMIMI -wiwewiwfw GJMPJH PK; PL

J. M. PUGMIRE 4July 20, 1965 ADDER 14 Sheets-Sheet 5 3 n0 00 00 D. 050.1 10 35 M 5 210 10 zum.. NM Du 1J 1 10 10 +|T 0 0 001 10 013 D| Dl 0600 nuo o0 Nw 3 301 10 ..10 2 Dl 0666 DI 2 1 10 10 10 |T|T|TIT 0 P 0 1001 10 1524 D... m e 6 01 0.1 01 10 MIDI P 2001101010 OOOOOAUN ZJ VT O 0000 00 .|1A 1|.. |d| Dl nl.. 110011010 |T|T|T1T|T|T nv o 0 10 10 01 101920.146 D.. nr n0 11 11 2 MM :JnUnU 00 55 D| v n 11 .1 201 10 P MFI 5 110 10 |T..T W 000 00 .oO n0 n0 G nu 7J 600 00 Dl zlv 3 .011 11 o O G G200 00 d. 1 1 o0 111 11 T Po G d. 1 000 00 D YZ V17.. V|7. nrnb 111111KD S :LR N N SE mw M WN UWM AH 11m NDUU N1V..C AT.. WMS mnrunuN Mc .10MD.. U MN CCW 0S rr. UHUN An Pv SF. mun

July 20, 1965 J. M. PUGMIRE 3,196,260

' ADDER Filed May 3, 1961 14 Sheets-Sheet 6 Flfsu F1G.9b

soa-3f f 91s X2 X30 X0 X20 Y1 July 20, 1965 .1. M. PUGMIRE 3,196,260

ADDER Filed May 3. 1961 14 Sheets-Sheet '7 No 951 z5 P5 FIG.9e

Y I i (4953 V954 FGJOCI Z6 P6 FIC-Mob lillllll llllllil July 2o, 196s 2J. M. Push/11m: 3,196,260

ADDER Filed May 5, 1961 14 Sheets-Sheet 8 FIC-).120

G G2 G2 P6 TTS ADDER Filed may s; i961 14 sheets-sheet 11 J. M. PUGMIREADDER 14 Sheets-Sheet l2 Filed May 3, 1961 J. M. PUGMIRE July 20, 1965ADDER 14 Sheets-Sheet 13 Filed May 5, 1961 1l 0 4 Il FIG.14e y UnitedStates Patent O 3,196,266 ADDER John M. Pugmire, Poughkeepsie, N.Y.,assigner to Enternational Business Machines Corporation, New York, N.Y.,a corporation or" New York Filed May 3, 1961, Ser. No. 167,495 11Ciaims. (Cl. 23S- 173) The invention relates to electronic bit-codeddigital adders and more particularly to a checkable adder whichgenerates a set of bit-by-bit summation functions logically from aplurality of applied operands and logically combines the summationfunctions to develop the sum.

The invention operates by generating bit-by-bit surnmation functionsaccording to symmetrical logical connectives of similarly weighted bitsin each of applied operands. The symmetrical logical connectives AND andOR of a particular bit weight of each operand form respective summationfunction terms G and P for the related bit weight. Where a particularweight bit, such as, for example, the 6 bit, is present in only onoperand digit, the appropriate term is P6. Where the 6 bit is present inboth operands, P6 and G6 .terms both are appropriate. Since G6 includesP6, the P6 term may be redundant, and, if redundant, is discarded.

Summation functions are available for all addition situations, such as(H-O, O-f-l, G-i-Z 9-}9. There are 55 addition situations for decimaldigit-s 0 9. Some summation funnctions cater to more than one additionsituation +1 and 4}2 in standard 2-out-of-5 code produce the samesummation function). The summation function in each such case correctlyindicates the sum.

. Elimination of the duplicate summation function circuitry andminimization of P and G terms allow `storedtable addition to take placein m-out-of-n codes without departing from the zii-out-of-n ratio of lbits to total bits. Basic checking of adder operation takes place on theadder output buses, by the ubiquitous validity check circuits whichadhere to major buses in modern computer systems.

Checking of electronic adders in prior art has generally followed twopatterns: duplication of adder circuitry with a final sum matching anderror detection when the sums do not match, and utilization of weightedvalue parity codes and comparison of the results with the predictedweight. High speed binary adders have been provided with simultaneouscarry propagation and generation which removes the necessity forallowing ripple time for the carries, but such adders have not beenreadily susceptible to parity checking. Parity bits have generally beendropped at the inputs to the adder and a new parity designation for thesum generated lafter passage of the operands through the adder. Sincethe adder is one of the most basic functional elements of a digitalcomputer, any error in the adder is likely to be magnified duringsubsequent arithmetic operations. The desire for maintaining a parityratio through the adder has been known but 'has not heretofore beendirectly realized.

The m-out-of-n code for binary bit coding of decimal digits has noparity bit included as such; the m-out-of-n codes, however, requireredundancy comparable to that of .the extra parity bit. This redundancyindicates single or triple errors in that, if a bit is dropped or pickedup, the bit structure will be (n2+1)-out-of-n or (m-1)-out 33 i $2Patented July 20, 1365 of-n which is easily decodable as an error.Adders for m-out-of-n codes are generally of the matrix or stored 1tabletype Since m-out-of-n codes do not exhibit any specitic logicalrelationship between numbers such as that found in pure binary codes.

A representative single-digit 2-ou-t-of-5 adder in the prior artincludes a 2-out-of-5 to 1outof10 decoder for each digit and a matrix ofone hundred magnetic cores placed at respective intersections of the tensignal lines representing an addend digit and the ten signal linesrepresenting an augend digit arranged at righ-t angles to one another.Since one addend line and one augend line are activated for eachaddition, the core at only one intersection is subject to coincidentcurrent and provides output. The core outputs are sampled by logicalcircuits to provide decimal outputs which are then encoded into therequired 2out-of5 code.

Such stored table adders are generally subject to a situation peculiarto themselves. If the addend is of value X and augend of value Y, theproblem is Y--V=Sum; if the values are interchanged, X+Y=Sum. Solutionof the problem X-l-Y--Sum is by mechanism distinct from that whichsolves Y-l-X=Sum.

According to this invention, stored-table addition is performed byreferencing the table according to summafion functions of the addend andaugend digits rather than by referencing the table according to theaddend and augend digits. Development of summation functions eliminatesthe distinction between Y-1-X=Sum and X4- Y=Surn- The object of theinvention, accordingly, is performance of stored-table addition basedupon summation functions of the addend and augend. Proper choice ofminimal summa-tion functions permits one and only one such function tobe activated when error-free information is processed.

Fewer than the valid number 'of bit variables fails to satisfy any ofthe minimal conditions. More than the valid number of bit variablesactivates more .than one member of the minimal set of summationfunctions.

Either occurence creates an output of an invalid form. No time is lostin checking; no additional mechanism is needed since bus parity checkmechanisms are standard equipment.

An object of the invention therefore is to maintain an m-out-of-n parityratio throughout addition.

Checked adders -in prior art operate by massive duplication ofcomponents. Any fault in either the adder proper or the check mechanismproduces one or a plurality of errors; the checking mechanism actuallyincreases the chances of fault. Prior checked adders are not readilysusceptible to faul-t localization by computer diagnostics. The checkingmechanism drastically impedes diagnostic techniques, since -a single setof errors can be caused by more than one fault possibility. A transistorfailure in the check mechanism, for example, may produce the samesymptoms as a transistor failure in the adder proper.

A feature of this invention in the combination of carry lookaheadmechanism, summation function generator and function combiner, whichprovide raw sum digits While maintaining m-out-of-n parity ratio, withcarry adjust mechanism and with carry check mechanism which compares thelookahead carry with the actual carry and adjustment. Carry faults,certain of which do not alter of interconnecting wires is a function ofspace. Asecond-circuitry, the speed-of-light delay in interconnectgingwires becomes a' limitation unless component packing is kept tight.:logic in the invention provides the advantage of a more compact adder.

v m-outofn validity, thus are detected, providing complete Qpowering-thecan drive only a fixed small number of Vtransistor inputs. 'circuitblock requires the same input as an adder proper circuit block, fan-outlimitations require duplication of In many instances, where la checkinginput register powering elements. i

Space in digital computers becomes vital, 1n that length In nano- Theelimination of large-scale checking l Fault elimination by eliminationof components is ap parent; the fewer components, the fewer are thechances vfor faults.

Fault V*detection becomes diflicult in circuit areas where an inputregister element drives more than one circuit element.` A single faultcanproduce Vseveral errors 1n 'such a situation; aparticular error canbe caused by 'each 'of yseveral possible faults.

be, able to pinpoint a particular fault as the cau-se of a particularerror; this allows computer diagnostic pro# It is an advantage to gramsto provide detailed Vrepair data. Downtime can th'us be minimized. It isa possibility, in prior art checked add'ers, to introduce delay into theadder-checker combination as a result'of the additional checkingmechanism. By maintaining the m-out-of-n parity ratio, this inventionprovides Dthe advantage ofcheckability by the standard bus paritycheckers, which introduces no eXtra delay.

An object of the invention is to provide an adder which `is subject tochecking by a-standa'rd equipment'validity checking mechanism.

A more particular'object of the invention is to Yprovide a specialfcheckupon between-digit carries.

VThe foregoing and other objects, .features and advantages oftheinvention will be apparent from the follow- Ving moreA particulardescription of a preferred embodi- `ment of the invention, asillustrated in the accompanying drawings.

In the drawings: p FIG. 1l 'is a block diagram of a'data processingsystem Vin which the adder of the invention operates.

FIG. 2 is a block diagram of a a'dder according to the invention.

FIG. 3 isV a block diagram of a single digit portion of the adder ofFIG. .2. I

'FIG.4 is a chart showing the bit structure of the inpreferredembodiment I struction word and of the dataword of the data processingisystem of FIG. 1.

FIG. isa chart of the 2-out-of-5 code bitf'structure. FIGS. 6a, 6b and6c are charts of the three basic fam- `ilies -of summation functions,Vwhich illustrate graphically the retention of the "aout-offriv ratio of1 to total bits. FIG.'7 is a chart of 'summation functions related tofdecimal operands and decimal sums.

FIG. 8 isa table ofvsummation Vfunctions related toV decimal operands.between X-l- Y=Sum and Y+X=Sum is made. Y

FIGS. 9a-9e schematically illustrate the true/complement vX-Z inputconverter and the P portion of the lsummation function term generator307 of FIG. 3.

The table shows that no distinction FIGS. 10a and 10b schematicallyillustrate the O- por- `tion of the -summation function term generator307 of FIG. 3. VIn 2-out-of-5 code, digits 1 9 are derived by i addingbit weights 0, l, 2, 3 and 6. Decimal 0 is the only digit not weightedtruly. Since the V0 decimal value in 2-out-of-5 code violates the bitweighting of the code, operands of zero value are pre-decoded.

FIGS. 11a and 11b schematically illustrate the G porv tion of thesummation function term generator 3&7 of

FIG. 3:.V

FIGS. 12a12h schematically illustrate within-digit carry -lookahead indetail.

FIGS. 13a-13e' schematically illustrate function combiner block 509 0fFIG. 3 in detail.

FIGS. 14a-14e schematically illustrate carry adjust .block 316 of FIGISin detail.

FIG. 15 schematically illustrates error checking circuits includingcarry duplicate block 311 and compare block 314 of FIG. 3 in detail.A

SUMMARY The adder in the preferred embodiment is of the simultaneouscarry parallel type. It ope-rates by generating 4-out-of-l() AND-ORsummation functions of the lbit-by-bit relationships of the 2-0ut-of-5coded decimal operands and by decoding combinations of AND-OR summationfunctions in a combiner to produce the 2-out-of-5 bit structure of thesum.

, Digit carries are produced in, a carry lookahead section and insertedin a carry adju-st logical level which alters the bit structureV of theraw sum from the combiner to a bit structure for the final sum. Thefinal sum includes effects of carries. The characteristics of them-out-of-n code are maintained throughout, although at one point Vthecode might more properly be thought of as 2moutof2n=. Single ortripleerrors are subject to Vparity checking on .the outputs. Aself-cancelling double error is not possible from a single fault. Thepredicted Y carry is checked against theV nal sum and raw sum bitstructures to determine whether the sum formed was greater than decimal9; i.e., whether a carry should have been produced. The adder thus notonly retains its 2- out-of-S error detection ability but also checksactual carvry against lookahead carry.

FIG. 1.-.S'ystem Adder V1111 accordingrto thel preferred embodiment ofthe'mvention operates well in the'context of a parallel ydata processingsystem. Registers 102-1il7 provide necessary instruction, result andoperand storage. Arithmeticreglster 102 is -connected via skew controlcircuitry `1G8 and 109 to'various full-word buses 111-114. Ad-

dress bus 115 and instruction counter 116 provide basic operationcontrol. Auxiliary register 103, instruction register 104, accumulator(l) 105, accumulator (2) 105 Y( and accumulator (3) 107 similarlyconnect to other regis- K ters and to adder'ltll via appropriate buses.

The ordinary add operation involves the arithmetic register` 192, adder101, accumulator 1) 10S and frequently one or both of Vthe otheraccumulators, for eX- ample accumulator (2) 106. With the augend storedin Y arithmetic register 162 and the addend stored in accumulator ('1),suitable gates operated under basic controlof the, mstruction counterland instruction register 104 -route the addendV via true bus 111 toadder 161 and route the augend via true/ complement bus 112 to adder191.V The sum .developed in adder lill passes via sum bus 113 and skewcircuitry 109 to arithmetic register 162 or .back to accumulator (l).

Validity check blocks 121, 122,"123 and 124 are associated respectivelyvwith true bus 111, true/complement Vbus 112, sum bus 113 and informationbus 114.V The Y' f preferred embodiment operatesrin.Z-out-of-S code,which is a popular representative of the Ym-out-of-n code family. Inm-out-of-Iz codes, the validityV check is a stringent check, sinceeither dropping 'or picking up a bit produces an error signal. All ls orall s on the bus produce a validity check. in all error situations,except the situation of exact compensation, where a particular bit isdropped and another bit picked up simultaneously, the validity check isabsolute.

Details of a suitable validity check circuit for 2-outof-S code areavailable in the following publication: IBM Customer Engineering, Manualof Instruction, 7601 A81? Control Unit, Section 2.3.04 Validity CheckCircuit, (FIG. 2.3-7), pages 24-25.

FIG. 2.-Adder The routing of augend and addend via true bus 111 (FIG. l)and true/complement bus 112 (FIG. 1) respectively to adder 101 (FIG. 1)was explained above under subhead FIG. 1.-System. rPhe appropriateportion of the true/complement bus 201 and the appropriate portion ofthe true bus 202 appear in FIG. 2. Carry lookahead circuits includedigit carry blocks (blocks C, 0, 1 9) 203 to 213, and include groupcarry lookahead blocks 214, 215 and 216. Lookahead carry signals and theoperand digits themselves are applied to adder blocks (C, 0, 1 9)217-227. The outputs of the adder blocks pass to portion 228 of the sumbus. Signals from adder blocks 217-227 also pass via carry check signalline 229 to carry check block 230.

The bit signals of the respective augend digits and addend digits areapplied simultaneously to carry blocks 203-213 and to adder blocks217-227. The carry blocks feed group carry lookahead blocks, whichproduce between-digit carry signals for the adder blocks as well asgroup carry signals.

The digit 4 stage of the adder is to be explained in detail infra. Carryblock 20S, group carry lookahead block 215 and adder block 222 areinvolved. To the el tent that the C OUT 6 signal from group carrylookahead block 216 affects carries from group carry lookahead block215, block 216 is involved.

FIG. 5.-Diga 4 Group carry lookahead block 301 is responsive to a carryout signal (C OUT` 5) together with a RQ signal at terminal 392, or to aRlO signal, to produce the digit lookahead carry signal C OUT 4. Digitcarry lookahead block 303 is responsive to G and P signals at terminalgroups 304 and 305. Relating FG. 3 to FIG. 2, group carry lookahcadblock 301 corresponds to a portion of group carry lookahead block 216and digit carry lookahead block 303 corresponds to carry block 203.Digit inputs for the augend are Y0, Y1, Y2, Y3 and Y6. Digit inputs forthe addend are X0, Xl, X2, X3 and X6. The addend digit is passed truefor addition or complement for subtraction by true/complement block3137', forming Z0, Z1, Z2, Z3 and Z6 at summation function termgenerator 393 where a summation function terms P, G, 0 and 0 aredeveloped. Summation function term P signals pass to summation functionterm combiner 309 where the bit structure of the raw sum R0, R1, R2, R3,and R6 is developed. The raw sum is applied to carry adjust block 310together with a carry signal (C OUT 5) at terminal 311. The inal sum bitstructure S0, S1, S2, S3 and S6 is the output of carry adjust block 310.The m-out-of-n relationship between l bits and total bits is maintainedthroughout the summation function generator 3&3, function combiner 309and carry adjust block 310. Any error will be detectable as a validitycheck on one of the buses, most probably the sum bus. A check on carryadjust block 310, however, must indicate whetheror not a carry outsignal (C OUT 4) is proper, since the m-outof-n relationship in thedigit 3 area will be maintained whether or not a carry out signal C OUT4 develops. Accordingly, the bit structure of the raw sum is monitoredin function combiner 3ii9 to produce an RlO signal on line 312 and thebit structure of the final sum is monitored in carry adjust block 310 toproduce an S10 signal on line 313. Carry duplicate OR (V) circuit 314passes a carry duplicate signal to compare block 315 where it iscompared exclusive OR (S) with the original lookahead carry signal (COUT 4) from group carry lookahead block 301 on line 316. Any mismatchbetween the lookahead carry and the duplicate carry signal produces anerror signal at error terminal 317.

FIG. JL-Word format The instruction word and also the data word of thepreferred embodiment includes ten digits 0-9 and sign. Each digitcomprises a 2-out-of-5 code bits 0, 1, 2, 3 and 6; the sign comprises2-out-o-3 code of 0, 3 and 6. The usual instruction word involves: anoperation code, digits sign, 0 and 1; an indexing word address, digits 2and 3; a field control designation, digits 4 and 5 and address, digits6-9. The instruction format is single address, indexed, fieldcontrolled. To add two numbers, three instructions are either requiredor inferred from past operations or future operations. The rstinstruction places one operand such as the addend in accumulator (l),105 FIG. 1. The second instruction reads out the second operand, forexample the augend, to arithmetic register 102, causes the two operandsto be applied to adder-101, and returns the sum via sum bus 113, skewcontrol logic 109 to arithmetic register 102 or back to accumulator (l)as required. In response to a third instruction, the sum fromaccumulator (l) 105, is stored in a designated address in memory.

FIG. .5.-2-out-of-5 code chart Conversion from decimal to 2-out-of-5code follows a standard weighted code logic. Bits are weighted 0, 1, 2,3 and 6. A combination of two of these weights can be developed for eachof the digits 1-9. The 0, however, violates the weighing rules. The 0combination is bits 1 and 2. Bit weightings, however, are not especiallysignincant in 2-out-o-5 code. There is no simple relationship, so far asbinary operating devices are concerned, between the 2 weight and the 3weight. The chart also includes a scale for the 9's complement. i

FIG. 6.-Summaton functions In addition, using 2-out-of-5 code, there areonly three basic families of combinations of the P (OR) and G (AND)summation function terms. FIG. 6a shows the functions for the additionof decimal 4 to decimal 2. Decimal 4 includes a 1 bit and a 3 bit;decimal 2 includes a 0 bit and a 2 bit. The P term, derived by takingthe OR function of 1 valued bits, is 11110, or Pi; Pi; Pk; Pl. The Gterm is 00000, since the bit structure of decimal 4 and decimal 2contains no similarly weighted 1 bits. The elimination of the problem oftransposed operands becomes quickly apparent. 1t makes no differencewhether the digit 4 is the Y or the Z, since the P and the G functionsare not affected by placement of the operands.

FIG. 6b illustrates the generation of the P and G function terms for theaddition of decimal 4 `and decimal 3, which belongs to the second familyof summation function terms Gj; Pj; Pk; Pl. Pj is a redundant term sinceGJ' includes Pj as a necessary operator. The decimal 4 bit structure01010, when ORed with the decimal 3 but structure lof digit Z (01'100)produces the ll term 011'10.

FIG. 6c illustrates the third family. Addition of decimal 4 to decimal 4produces G terms for the weight 1 bit and for the weight 3 bit and, ofcourse, P terms for the weight 1 bit and weight 3 bit. It is to be notedthat four decimal digits 04-6 (sum=6).

' ,combiner itself comprises a minimal set of summation "function terms,each member of which belongs to one of these catagories:

GJ' (rj) P] Pk Pj Plc PZ Theterms in parentheses are deleted because ofre-V dundancy. A valid number of Gi, Pz', inputs will energize one andonly one member of the minimal set; the output encoder of the combinerwill produce a m-out-of-n raw sum digit. Greater or fewer than thecorrect number of variables will energize no members or more than onemember of the minimal set, and hence providey an output violating them-out-of-n requirements. The combiner ,thus provides a checkedtransition from a (checked) 2m-out-of-2n code to a (checked) m-out-of-ncode.

FIG. 7.-Summatin function chart Where digits Y and Z are each 4, the Pterm is 01010 and the G term 01010. Since 4-i-4 equals 8, thecombinav.tion summation function Gl, G3-produces a raw sum Where digit Yis 7 and digit Z is 8, the P summation ,function term is 01101 and the Gsummation function Aterm 00001. 7-1-8 equals l5 as does 8+7 equal 15..-Summationfunction G6, P1, P2, produces raw sum with a carry indicatedby an asterisk t. v Addition of decimal digit l to decimal digit 9produces l P term 11011 and G term 00000, as does addition of 9-1-1,3-1-7, 4+6, 7-1-3 and 6-|4. Summation function P0, P1, P3, P6 producesraw sum digit 0 with a carry (0*).

Three situations existwhere summation functions are identical althoughdifferent sums exist. These situations all occur in the Pi; Pj; Pk; Pl;family. For example, addi- Y tion of decimaldigits l-i-S or 2-1-4 (sumz)produces A the P function 11110 and the G function 00000. Summationfunction terms P0, P1,'P2 and P3 are produced.V Addition of decimaldigits 0-l-3 (sum=3) also produces the same 'P andV G functions. Thusthe summation terms P0, P1, P2 and 'P3 may indicate either the sum 6 orthe sum 3.. The same situation exists in the addition of decyimal digits1+8 or 2-1-7 (sum=9) and the addition Vof YBoth produce the summationterm P0, P1, P2, P6. YThe third'ca'se is in the addition of decimaldigits 4-5-8 or 5+7 (sum=2=) andV `the addition of 0-1-9 (sum-:9). Bothproduce summation terms P1, P2, P3, P6. It will be noted that in each ofthese three cases, one of the additionsV producing the ambiguoussummation terms involvesl an addend or augend i equal to 0. Properidentication of the summation terms for the dilferent sums may thereforebe accomplished by Yaddingan `additional term' tothe summation functionterms, this term being 0 or 0. Where either the addendV or augend is 0the summation function term 0 is used with the ambiguous termV Pi, Pj,Pk, Pl and when neither addend nor augend equals 0 the function term isused. The means for `generating thegO- function lterm isidescribed laterherein with reference to FlG. 10.

The summation function P terms which are included in il Gterms arediscarded as redundant. T he'chart shows a v contain duplicate summationfunctions.

.tinct summation functions suice forthe preferred emment.

FIG. 8.--Summato-n function' table A minimal summation function can begenerated for eachV addition. Addition of O|0 for example, producesfunctions G1, G2, P1 and P2. Since terms'Gl and G2 include respectivelyterms P1 and P2, the zero sum can be decoded directly from` function Gl,G2. FIGURE V8 shows the functions selected for the preferred embodi-Addition of (3-1-1) or of (1|3), for example, produces the raw sum 4which is decoded as the summation function (combinationof terms) G0, P1and P3. The term P0, which is inherent in G0, is discarded as redundant.

Redundant terms are eliminated throughout. This reduces the number ofcomponents necessary by holding Vfan-out from each input register toaminimum. The

chance for fault compensation (for example, a redundant P0 connectionmight mask Ia faulty G0 connection) is thus eliminated. Y

The total number of summation functions required, as shown by the table,isV 5,5 for addition of two'decimal digits. Symbols within blocksindicate 7 occurrences Vwhere additions of diiferent digits produceidentical sum- 'mation functions and identical sums.` Diagonally alignedblocks having the same symbol (ball, diamond, square) Thus, 48disbodiment. FIGURE 8 is further explained infra in connection with thediscussion under subhead FlG. 13.- Function combiner, togetherwith theactual mechanism for producing the summation functions.

FIG. 9.True/c0mplemenz input converter-P generator The adder ofthe-preferred embodiment is constructed of Vtransistor stroke blocks.The stroke block functions -as an ANDinverter for a positive input; itfunctions as an OR inverter for negative inputs.-

Depending upon the polarity of output which produces ay functionalsignal, identical stroke blocks may be designated AND circuits or -ORcircuits. Representatives of stroke blocks are the circuitssometimes'called` NOR, (Not OR) and its close relative NAND (Not AND);all provide the charac- 902 is connected to ground and'via outputresistor 903 to a source of voltage at -12. The baseof transistor 902'is connected via resistance 904 to a source of voltage at +12.Transistor 902 is jnormally held cut olf, producing at terminal 906 "anoutput voltage of -'-s. -s

i Equals -6 volts due torclamping diodeV 907 which connects terminalv906to a regulated source Vof voltage at -6 volts. If any input totransistor 902 is negative, a

l negative bias via an input resistance such as 905 forward biasestransistor 902, raising the Voltage at terminal 906 to approximatelyground potential, +S. Only when all inputs to transistor 902 are -l-sdoes transistor 902 cut off;

- it functions as an AND inverter or as a -`OR. The characteristics or"circuit components normally used make an input fan of Ythree or fewerVadvisable for theordinary single-transistor stroke block. To produceinput fans greater than 3, additional transistors such as 908- areconnected commonl collector with the basic stroke block transistor 902vto share output resistorz903faud function as Y for'greater fan-out. mentdrawings FIGURES 9-715, stroke blocks are shown a six-input strokeblock. Additional transistors can be schematically as trianglesregardless of the input and output fans.v Y

Inputs to block 901 are X0 and T. T is the signal for true add. Otherstroke blocks inputs are X2, X6, C; X0, X3, C; X0, X6, C; X1, X6, C; andY0. The output of block 914 is Z0, where Z is the digit resulting fromthe true or complement digit X0. Block 901 produces the Z0 term directlyfrom the XO term and the true signal. Blocks 909-912 produce the Z0 termduring complement situations. Block 909, for example, produces a -ssignal upon the coincidence of the X digit 8 and a complement signal C.The FIGURE chart shows that the complement of 8 does not contain aWeight 0 bit, as does the complement of '7 and the complements of 6 and3. Block 910 is conditioned by XO, X3 (decimal 3) and C to produce theZ0 signal via block 914. Block 914 functions as an OR circuit for the -soutput of block 910. Similarly blocks 911 and 912 produce the Z0 outputvia block 914 upon coincidence of decimal digit 6 bit values and C anddecimal digit 7 values and C respectively.

Block 915 produces the P0 signal, which is the OR function of 1 bits atweight 0 (Y0 or Z0) of operands Y and Z. Inputs to block 91S areidentical to those of block 914 with the addition of a Y() term fromblock 913.

FIGS. 9b-9e are similar in all significant respects to FIGURE 9a. Block916 produces the Z1 signal upon coincidence of X1 and T; blocks 917,909, 918 and 919 produce the Z1 signal upon detection of bit structuresfor those decimal digits whose 9s complements include the 1 bit. Block920 introduces the Y1 bit which is a part of the P1 term. Blocks 921 and922 respectively produce the terms Z1 and P1. Block 909 is shown dottedin FIG. 9b. To make the logic more apparent, the circuits for producingZ and P terms for each of the live bit weights are shown entire; eachbit Weight Z and P function term generator is a separate FIGURE 9ct-9e.Where a term such as X2, X6, C is common to more than one bit Weight,the output of a single stroke block such as 909 is tanned out to eachatected bit. To avoid confusion of criss-crossed lines in the drawings,the stroke block is shown dotted to indicate that it appears elsewherein the figures and the reference number of the first appearance is used.

The circuits in FIGS. 9er-9e produce terms Z0, Z1, Z2, Z3 and Z6 as wellas summation functions P0, P1, P2, P3 and P6. These terms and functionsare available wherever required by circuits throughout the preferredembodiment.

FIG. 10.-0-5 Summazon function generator FIG. 10b illustrates thedecimal 0 term generator; FIG. 10b illustrates the decimal termgenerator. The circuits in FIG. 10a and 10b are identical except for afinal inverter in FIG. 10b. It is not advisable, however, to conservestroke blocks in this area by using the common output techniques such asthose used in FIGURE 9, since a failure in the 0 5 area could otherwiseoccur undetected. The 0 decimal value occurs in three situations. Strokeblock 1001 produces the 0 signal when Xl and X2 bits (decimal 0) arepresent when adding true. Block 1002 produces the 0 signal when bits X3and X6 are present and the C signal appears, because the complement ofdecimal 9 is 0. Block 1003 produces the O signal when digit Y is adecimal 0. Block 1004 functions as a OR circuit to produce a -i-s 0functional signal. In FIG. 10b, blocks 1011-1014 are identical in inputand function to blocks 1001-1004, respectively, to produce the decimal 0signal at the output of block 1014. Inverter 1015 inverts to the notdecimal 0 signal, or 0 signal.

FIG. 1].-Summation function Gi generator For any particular bit weight,such as for the 6 Weight, as illustrated in FIG. 11a, the G function isgenerated by an AND circuit followed by an inverter. Stroke block 1101produces the G6 signal at its output with inputs Y6 1@ and Z6. Block1192 invertsto G6 and provides the G6 signal as an input to sum strokeblock 1103a .which receives the G6 signal. A peculiarity of stroke logicis that, in situations such as this, it is just as etective to feed theoriginal Y and Z terms as a bundle into the receiving block 1103 (FIG.11b) as to feed the inputs through stroke blocks 1101 and y1102. Gi,then, is available as a bundled pair of Yi and Zi lines connected asinputs to any receiving stroke circuit 1103b. Gi is available, as Gb inFlG. 11a, from stroke block 1101. Where fan in and fan out problemsoccur, it often is just as effective to follow the more straightforwardtechniques of 11a, but where the receiving logic makes it possible it isoften advantageous to utilize the G'-signal or the bundling technique.

FIG. 12,-Carry Iookahead Stroke blocks 1201-1206 combine to produce thedigit generate term DG. (Block 1201 is generally not necessary since itsoutput is G6, a term which is available from the circuit of FIG. 11a.)G6 occurs only when the addition is of decimal values each of whichincludes the bit weight 6, i.e., 6, 7, 8 or 9. A carry always occurs insuch additions. Block-1206 functions as an OR cir-cuit to generate theDG term.

Block 1202 indicates a carry produced by addition of 5-l-5, the onlysituation where G2, G3 occurs.

Block 1203, with inputs including G2, P6, indicates a carry foradditions of decimal 8 and a 2 weight-8+2; S-l-S 8-l-8. Since the digit0 includes a 2 Weight, the 0 term is included as input to eliminatecarry production in addition of S-l-O.

Block 1204 is subtle. as follows:

It indicates a carry for additions The derivation of this carry is mostsimply explained inductively. The P3, P6 inputs indicate a Weight of atleast 9. The input eliminates the possibility of the 9+() addition whichproduces no carry. The output of block 1205, YOZO, eliminates thepossibility of the 6+?, addition which produces no carry. All otherpossibilities produce carries. Block 1206, therefore, produces the carrygenerate term DG Whenever Y-t-Ztl.

FIG. 12b produces the carry propagate term DP whenever Y+Z=9 and in manycases Where Y-t-Z 9. Block 1210, with inputs P6, P3, indicates a weightof at least 9, derived from additions 9-l-(any digit) and from additions(6 or greater){-(3 or greater). Block 1211 indicates a weight of atleast 9 in additions 7-1-2, 8-5-1, 8-l-4, etc. Block 1212 indicates aWeight of 9 in addition of digits 5+4.

The terms DP and DG are combined in carry lookahead circuits accordingto standard procedures for simultaneous carry production. See, e.g.,U.S. Patent 2,879,001, Simultaneous Carry Adder, Weinberger et al.,issued March 24, 1959, for exhaustive treatment of DP, DG carrydevelopment. Details of carry lookahead circuits a-re shown in FIGS.12C-12h, and discussed briefly infra, for convenience in understandingthe entirety of the adder.

FIG. 12e illustrates carry lookahead. Carry into any order is developedby a carry generate term DG from the previous order or by a combinationof a carry propagate term DP from the previous order plus a carry intothat previous order. For example, Cin8=DG9+DP9, Cin9.

FIG. 12C shows blocks 1219-1246 which function to produce simultaneouscarries for digit positions C, 0, 1 9. Blocks 1219-1229 are DG, DPblocks for the related digit positions C, 0, 1 9. These blocks producesignals whenever either a DG or a DP term is available. The outputs ofblocks 1219-1229 are available to group lookahead carry blocks 1230-1235and FP. lines.

directly upon coincidence of the output of DG, DP block 9 (1229) and thecarry in 9. The carry out of lookahead YVcarry 8 (1235) 'isl connectedto lookahead'carry, 6 block k1245 and lookahead carry 7 block 1245.Block 1246 is eitectively a logical AND circuit coincidently conditionedby the outputof lookahead 8 block 1235 and byDG, DP

"block 1228. `As embodied, block 1246 is conditioned by "DGS or (DPS)CinS. The DG and DP outputs have been consolidated on one line forsimplicity. It is desired to carry into position 7 wheneverv position 8generates a carry(DG8) or Whenever position 8 propagates a carry (DP9,Cin9).

The logic for other lookahead carries is as follows: Cins=DG9+DP9,YCinaY DPS) CinS: (DGS-5) -I- (DPS-5) CinS DPo,Dr 1) (DG2+DP2, DG3,DG4+DP2, Drs, DP4, DG5)+(DPC, Dro, DP1 (DPz, Drs, DP4, DPS) cins.

As shown above, carry into anydigit position is a functionof a carrygenerate term DG from the previous position or ay combination of a carrypropagate term DP from For erally provided in groups, and the grouplookahead carries introduced at a final stage AND (-OR) circuit1236-1246 to provide the actual carry in signals.

For floating point operations, it is desirableY to treat positions and 1as the characteristic of a floating point number. ln the oating point ofthe usual type, the

rdecimal point is always placed at the left of the most signitcantnon-zero Vdigit in the mantissa. The characteristic is then the power of10 which will raise or'lower 1 the value of the mantissa to thedesired-level. Because it is desired to work in both fractions and wholenumbers,

- it is common to modifythe characteristic by 50, that is, to v assignthe characteristic value -50 to the value (10).

This allows the characteristic-to be handled by simple Y addition Vandsubtraction but still remain a-wholenumber over the range (10)"49 to(l0) +49.

The facility is Yprovided for anticipatory end-around carry for theO-lrpositions'during Floating Point.' The selection for thisV carryinsertion is made by the RB., No

FIG.v12d.-Carry loorkzzhead card The carry lookahead circuits are laidout so that identical cards make up the circuit. One card appearsin4FiG.

SFrG. 12d-Dran Y FrG. ize-DPo-z VYof the digit-4 adder.

produce sumssmaller than 1t),l generating no carry.

VruG. tze-DPVC-l 12d indetail; four othercards appear in FIGS. 12e, 12f,

. 12g and 12h as block diagrams of circuits identical to `those on the,cardv oiv FG. 12d, with inputs and outputs detailed.

Blocks 1250-1263 make up card 1264. Cards 1265- 1268 are identical tocard 1265. Block 1256 forms an AND circuit for up to iive inputs. Otherblocks1252- "1262 serve as AND circuits; the outputs of the AND circuitsfeed -OR circuitsf12511263.

The OR circuits produce outputs as follows:

Cin() Cinl DG() Cin5 Cin6 Cin7 Y DG2-5 Cin3 Cin4 DGS-5 COUT Cin2 DGC-lCinC Cin8 The lookahead carry cards fulllthe functions assigned to themas explained inV connection with FIG. 12C,V supra.

FIG;13.-Fzmcti0ncombiner `Functions are combined in straightforwardvrfashion. Gi, Pz', O'and termsin appropriate combination formrsummation function-signals according tothe chart in FdG. 8. VThesesummation function signals are applied to multi-input OR blocks toproduce weight bits of the raw sum, R0, Rl, R2, R3-an`d R6, asappropriate. Weight bits R0, for example, occur in the following digitsums: (see PEG. 5) V1, 2, 3, 6, 11, 12, 13-and-16. Weight bits R1 occurindigitrsurns-O, 1,'4, 7, 10, 1l, 14 and 17.

FG. 13a illustrates the function combiner RO-section Strokebloclis11311319 are involved. Block- 1319 isa multi-input-OR block topass the RO signal for all summationl function combinations which are tocontain the weight O bit inthe raw sum.

Block 1391 functions during the 1}1 addition, where terms G0 and G1appear. The sum is-to be 2, which, in Z-Qut-of-S code is a weight 0 bitand-a weight 2bit'. Block 13111 output signal, -s for the G0, G1summation function, conditions a transistor in stroke 1319, whichconducts, bringing the output of block 13119 to -l-s or groundpotential, which is the RO'signaL Block 1392 functions similarly toblock 1301, producing a s output for the 3-1-3 addition (GO, G3) whichin 2- out-of-tS code produces vthe digit sum 6'as a weightO bit and aweight 6 bit. Block 131g functions as a -OR Inverter block, producingthe -i-s signal RO.

Blocks.` 1363-1318 in-FIG.'13a similarly operate to produce weight O bitsignals via block1319 for respective sums 6, 3, 6, 1, 2 and 3 asdetermined by theapplied summation function terms. Block 1303 iseffective-for additions l-l-S and 2|4 which produce thesum 6. BlocksV1341and 1305 include 'the 0 term as input to produce weight 0 bits R0in respective additions 3+() and 6-\-0. Blocks 1MB-137118 ,recognizesummation functions which Blocks 13119-131 produce sum digit eight Obits for lrespective,additions 6+h6; 8-1-78; 2-t-9 or 3|8 or.5+6; 4+8 or5 1-7; 4-1-7; 3-1-9; 4-i-9; 5-1-8; 6-{-7 and 7-1-9. In each oftheseadditions there is to be a carry out.

VEach block 1361-1318 in FIG. 13a has an output arrow labeled 12.1', R2,R3 or R6. Thisy arrow indicatesa fan-out A ,to the -'-OR block whichproduces therappropriateweight bit. 1 For convenience in understanding,the entire block is shown (dotted) in the appropriate weight bitfunction combiner circuit. For example, block 17313 combines terms G1,P6, P3 Vfor the 7-1-4 addition sum 1 and carry. Block 1313 outputbecomes input to R0 OR block 1319 and also to Rl ()Rblock 1335 in FIG.13b, toproduce the l'digit raw sum in the form (R0, Rl) called for bythe summation functionsV for digit sums including the-weight. 1 bit are;applied in appropriate combinations to. blocksV

9. A 2-OUT-OF-5 CODED COMPUTER SYSTEM COMPRISING: (A) A FIRST OPERANDBUS; (B) A SECOND OPERAND BUS; (C) A SUM BUS; (D) A VALIDITY CHECK MEANSASSOCIATED WITH SAID SUM BUS FOR SIGNALLING ERROR UPON DEFAULT OF2-OUT-OF-5 CODE RULES, AND (E) AN ADDER CONNECTED TO SAID FIRST OPERAND,SECOND OPERAND AND SUM BUSES FOR PRODUCING A FINAL SUM ON SAID SUM BUSIN 2-OUT-OF-5 CODE IN RESPONSE ADDED COMPRISING: (A) CARRY MECHANISM FORPRODUCING CARRY DESIG(A) CARRY MECNANISM FOR PRODUCING CARRYDESIGNATIONS IN RESPONSE TO CARRY OUT SITUATIONS FROM PREVIOUS ORDERS;(B) A SUMMATION FUNCTION TERM GENERATOR FOR PRODUCING LOGICAL AND AND ORCORRELATIONS BETWEEN EQUAL WEIGHT ADDED AND AUGEND 2-OUT-OF5 BITS ASFOLLOWS: